A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs
نویسندگان
چکیده
The number of embedded cores in an FPGA has been increasing and different devices use different numbers of different types of hard IP cores. To facilitate failure analysis and reduce its turnaround time, we present an automated BIST-based methodology that exploits the existing redundant resources of an FPGA and its reconfigurabilty to efficiently locate the faulty IP block(s) in addition to pass/fail test. It doesn’t impose any area overhead, cost, or performance degradation and it is applicable to different types of cores and scalable for different devices.
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